1 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com EDI8L32128C december 2000 rev. 5 eco #13525 128kx32 cmos high speed static ram features 128kx32 bit cmos static random access memory array fast access times: 12, 15, 17, 20, and 25ns individual byte enables user configurable organization with minimal additional logic master output enable and write control ttl compatible inputs and outputs fully static, no clocks surface mount package 68 lead plcc, no. 99 (jedec mo-47ae) small footprint, 0.990 sq. in. multiple ground pins for maximum noise immunity single +5v ( 5%) supply operation description the EDI8L32128C is a high speed, high performance, four megabit density static ram organized as a 128kx32 bit array. four chip enables, write control, and output enable provide the user with a flexible memory solution. the user may independently enable each of the four bytes, and, with minimal additional peripheral logic, the unit may be configured as a 256kx16 or 512kx8 array. fully asynchronous circuitry is used, requiring no clocks or re- freshing for operation and providing equal access and cycle times for ease of use. the EDI8L32128C, allows 4 megabits of memory to be placed in less than 0.990 square inches of board space; a savings of 0.885 square inches over four standard 128kx8 components. note: solder reflow temperature should not exceed 230 c note: pin 2 & 67 on the 64kx32 (edi8l3265c) and the 256kx32 (edi8l32256c) are word select pins. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dq17 dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq14 dq13 dq12 vss dq11 dq10 dq9 dq8 vcc dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 dq31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a6 a5 a4 a3 a2 a1 a0 vcc a13 a12 a11 a10 a9 a8 a7 dq0 9 dq16 8nc 7nc 6e3 5e2 4e1 3e0 2nc 1 vcc 68 nc 67 nc 66 g 65 w 64 a16 63 a15 62 a14 61 dq15 block diagram a 0 - 16 g w e0 e 1 e 2 e 3 dq 0 -dq 7 dq 8 -dq 15 dq 16 -dq 23 dq 24 -dq 31 128k x 32 memory array 17 fig. 1 pin configuration pin description a ?-16 address inputs e ?-3 chip enables (one per byte) w master write enable g master output enable dq ?-31 common data input/output v cc power (+5v 5%) v ss ground nc no connection top view
2 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com EDI8L32128C december 2000 rev. 5 eco #13525 absolute maximum ratings* recommended dc operating conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (f = 1.0mhz, v in = v cc or v ss ) 30pf 480 ? vcc q figure 2 figure 3 255 ? 5pf 480 ? vcc q 255 ? ac test conditions dc electrical characteristics voltage on any pin relative to v ss -0.5v to 7.0v operating temperature t a (ambient) commercial 0 c to + 70 c industrial -40 c to +85 c storage temperature -55 c to +125 c power dissipation 4 watts output current. 20 ma junction temperature, t j 175 c parameter sym min typ max units supply voltage v cc 4.75 5.0 5.25 v supply voltage v ss 000v input high voltage v ih 2.2 -- v cc +0.5 v input low voltage v il -0.3 -- 0.8 v parameter sym max unit address lines c a 40 pf data lines c d/q 10 pf write & output enable lines w, g 40 pf chip enable lines/byte select e 0-3 8pf truth table e w g mode output power h x x standby high z i cc2 ,i cc3 , l h h output disable high z i cc1 l x x output disable high z i cc1 l h l read d out i cc1 l l x write d in i cc1 parameter sym conditions typ max units 12* 15 17 20/25 operating power supply current i cc1 w= v il , i i/o = 0ma, 620 720 680 640 600 ma min cycle standby (ttl) supply current i cc2 e v ih , v in v il or 160 160 160 160 ma v in v ih , f = mhz full standby cmos supply current i cc3 e v cc -0.2v 20 v in v cc -0.2v or 20 20 20 ma v in 0.2v input leakage current i li v in = 0v to v cc 10 a output leakage current i lo v i/o = 0v to v cc 10 a output high volltage v oh i oh = -4.0ma 2.4 v output low voltage v ol i ol = 8.0ma 0.4 v input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 2 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 3) typical: ta = 25 c, v cc = 5.0v
3 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com EDI8L32128C december 2000 rev. 5 eco #13525 ac characteristics - read cycle symbol 12ns 15ns 17ns 20ns 25n parameter jedec alt. min max min max min max min max min max units read cycle time t avav t rc 12 15 17 20 25 ns address access time t avqv t aa 12 15 17 20 25 ns chip enable access time t elqv t acs 810172025ns chip enable to output in low z (1) t elqx t clz 23333ns chip disable to output in high z (1) t ehqz t chz 7 8 8 10 10 ns output hold from address change t avqx t oh 33333ns output enable to output valid t glqv t oe 568810ns output enable to output in low z (1) t glqx t olz 22220ns output disable to output in high z(1) t ghqz t ohz 456810ns note 1: parameter guaranteed, but not tested. a q t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz g e fig. 5 read cycle 2 - w high fig. 4 read cycle 1 - w high, g, e low a q t avqx t avqv t avav data 2 address 1 address 2 data 1
4 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com EDI8L32128C december 2000 rev. 5 eco #13525 fig. 7 write cycle 2 - e controlled fig. 6 write cycle 1 - w controlled a d t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z w e q g t glax symbol 12ns 15ns 17ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units write cycle time t avav t wc 12 15 17 20 25 ns chip enable to end of write t elwh t cw 8 9 10 15 20 ns t eleh t cw 8 9 10 15 20 ns address setup time t avwl t as 00000ns t avel t as 00000ns address valid to end of write t avwh t aw 9 10121515ns t aveh t aw 9 10121515ns write pulse width t wlwh t wp 9 10121515ns t wleh t wp 9 10121515ns write recovery time t whax t wr 00000ns t ehax t wr 00000ns data hold time t whdx t dh 00000ns t ehdx t dh 00000ns write to output in high z (1) t wlqz t whz 05060 707010ns data to write time t dvwh t dw 568812ns t dveh t dw 568812ns output active from end of write (1) t whqx t wlz 22222ns ac characteristics - write cycle note: parameter guaranteed, but not tested. a d t aveh t eleh t ehax t dveh t ehdx t avav data valid high z w t wleh e q t avel
5 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com EDI8L32128C december 2000 rev. 5 eco #13525 package description package no. 99: 68 lead plcc jedec mo-47ae commercial (0 c to +70 c) part number speed package (ns) no. EDI8L32128C12ac 12 99 EDI8L32128C15ac 15 99 EDI8L32128C17ac 17 99 EDI8L32128C20ac 20 99 EDI8L32128C25ac 25 99 ordering information industrial (-40 c to +85 c) part number speed package (ns) no. EDI8L32128C15ai 15 99 EDI8L32128C17ai 17 99 EDI8L32128C20ai 20 99 0.180 max 0.115 max 0.040 max 0.050 bsc 0.020 0.015 0.930 0.890 0.956 max 0.995 max 0.956 max 0.995 max all dimensions are in inches
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